1. Field of the Invention
The present invention relates to a method of reducing a measuring time during an automatic measurement of integrated circuits (ICs) mounted on test stations which are arranged in parallel with one another.
2. Prior Art
An IC tester for testing ICs includes a plurality of IC testing or measuring parts (hereinafter referred to as test stations) on which the integrated circuits (ICs) are mounted. In case of testing a plurality of ICs at a time, modes for outputting the same test signals between respective stations at the same time (parallel mode between stations) are set for testing the ICs mounted on each test station. Further, automatic carriage means for automatically supplying ICs to be tested (hereinafter referred to as handlers) are connected to respective test stations so as to automatically supply the ICs to and accommodate the ICs in respective test stations.
A state of connection between the IC tester, test stations and handlers is illustrated in FIG. 3. In the same figure, denoted by 1 is an IC tester, 2A to 2D are test stations, and 3A to 3D are handlers. The IC tester 1 includes an external device control circuit 1A and a computer 1B.
Suppose that there are four test stations 2A to 2D and our handlers 3A to 3D are respectively connected to the IC tester 1. The IC tester 1 generally comprises a plurality of test stations and handlers respectively connected to the test stations. The number of the test station may be two, three or more than five. Each handler supplies a test start request interruption signal to the external device control circuit 1A of the IC tester 1 when the IC to be tested has completed the preparation for the test, namely, when the IC is ready for the test.
In FIG. 3, the test stations 2A to 2D are respectively connected to the handlers 3A to 3D, and the handlers 3A to 3D are respectively electrically connected to the external device control circuit 1A of the IC tester 1. The computer 1B processes signals issued from the handlers 3A to 3D to the external device control circuit 1A.
When the handlers 3A to 3D are used, a test start request relative to the IC tester 1 is carried out to start the test not by a switching operation by an operator who handles the IC tester but by a software process comprising the steps of issuing the test start request interruption signals from each handler to the IC tester 1, and receiving the test start request interruption signal by the external device control circuit 1A of the IC tester 1.
Since all the handlers connected to the IC tester 1 are not always operated in synchronization with one another, but issue the test start request interruption signals separately to the external device control circuit 1A of the IC tester 1, the test stations 2A to 2D do not complete the preparation for the test at the same time.
In order to reduce the test time by increasing the number of test stations for executing the test at the same time, the IC tester 1 waits a fixed time until the test start request interruption signals are issued from the plurality of handlers to the external device control circuit 1A.
The computer 1B reads the test start request interruption signals issued from each handler for verifying from which handler the test start request interruption signal is issued. Upon verification of the test start request interruption signal, the external device control circuit 1A waits for test start request interruption signals issued from remaining handlers which are respectively set or arranged in parallel with one another for testing.
Since a wait time is set or measured by the IC tester 1, if the test start request interruption signals issued from the remaining handlers are not received by the external device control circuit 1A within the set wait time, the test is executed by the test stations which are connected to the handlers from which the test start request interruption signals are issued. During the execution of test, the test start request interruption signal from the handler is held, and the test execution wait condition continues until the first executed test is completed.
The operation of the conventional method of testing ICs of FIG. 3 will now be described with reference to a flow chart of FIG. 2. FIG. 2 shows an operation of starting a test after the external device control circuit 1A of the IC tester 1 waits for a fixed time until it receives test start request interruption signals issued from the plurality of handlers 3A to 3D, particularly, FIG. 2 shows the operation when the test stations 2A to 2D are set or arranged in parallel with one another for testing.
In Step 11 of FIG. 2, the external device control circuit 1A receives a test start request interruption signal from any one of the handlers 3A to 3D. In Step 12, the computer 1B judges whether this test start request interruption signal is the first interrupt, and an interruption wait timer starts to count the wait time in Step 13 if the test start request interruption signal is the first interrupt.
Suppose, for example, that the test start request interruption signal is first issued from the handler 3A connected to the test station 2A, the external device control circuit 1A receives the test start request interruption signal and verifies from which handler the test start request interruption signal is issued, and the interruption wait timer starts to count the wait time.
The wait time is set in advance by a setting part, etc., not shown. In Step 15, it is judged whether the previously set wait time has lapsed or not, and if the wait time has not lapsed, a wait condition continues.
During the continuation of the wait condition, the external device control circuit 1A receives the test start request interruption signals from other handlers wherein the test start request interruption signals from other handlers are subject to the processes in Steps 11 and 12. If the test start request interruption signal is not the first interruption in Step 12, and hence it is subject to the process in Step 14.
In Step 14, it is judged whether there are interrupts from the handlers connected in parallel with the IC tester 1. If there are interrupts from all handlers, the test is executed in Step 16 regardless of the lapse of the wait time in Step 15.
If there is no interrupt from all the handlers, the program returns to a step before Step 11 where the external device control circuit 1A waits to receive the test start request interruption signals from other handlers until the lapse of the specified wait time in step 15. For example, if the test start request interruption signals are issued from the handlers 3B and 3C in a previously set wait time, the external device control circuit 1A verifies from which handlers the test start request interruption signals are issued and further waits the start of the test.
If the set wait time lapses in Step 15, only a test station connected to the handler from which the test start request interruption signal is issued to the external device control circuit 1A starts the test without waiting for the issuance of the test start request interruption signals from the remaining handlers. The test is executed in a state where the handlers 3A to 3C are arranged in parallel with one another.
If the test is executed in Step 16 owing to the lapse of the specified wait time in Step 17, the external device control circuit 1A only verifies the handler 3D but holds interrupt based on the test start request interruption signal from the handler 3D even if the handler 3D issues the test start request interruption signal to the external device control circuit 1A after executing the test.
If the test is completed by the test stations 2A to 2C in Step 18, the external device control circuit 1A receives the test start request interruption signals issued from the remaining handlers in Step 19, and the processes in Step 11 and succeeding steps are repeated, then a next wait time is counted by the wait timer. The handler, which completed the discharge of the tested ICs and the supply of the ICs to be tested next time upon completion of the test by the test stations 2A to 2C, issues again the test start request interruption signal to the external device control circuit 1A.
Likewise, if the external device control circuit 1A receives the test start request interruption signals from all the handlers, the test is executed at that time. Even if the external device control circuit 1A does not receive the test start request interruption signal from one or more handlers, the test is executed at the time when the wait time set by the wait timer lapses.
In case of testing ICs by the test stations which are arranged in parallel with one another in the structure of FIG. 3, if the test start request interruption signal is issued from the handler immediately after the start of the test in the processes of FIG. 2, the test station connected to the handler which issued the test start request interruption signal immediately after the start of test holds the test until the next test since the wait time set by the IC tester is held constant, causing a problem that the test time is wasted.
Further, in case that the handlers do not issue the test start request interruption signals because of trouble or the like, the external device control circuit 1A waits the issuance of the test start request interruption signals until the lapse of the specified time, which also causes a problem that the test time is wasted.